We are trying to get LEPTON VoSPI working with our FPGA hardware.
I have two questions here.
1. Is CRC data valid if the packet is invalid? Does invalid packet or discard packet carry valid CRC information?
2. How soon post de-assertion of CS + 200ms gap with SPI_CLK idling and then asserting CS and SPI_CLK, we will start getting valid frames?
We are trying to pass constant data to check validity of VoSPI capture and for almost 4-5 frames, we could not get valid constant data.